The present invention relates to a NAND flash memory device having a memory cell array in which a plurality of electrically-rewritable memory cells are arranged in a matrix pattern.
The NAND flash memory device has a memory cell array in which a plurality of electrically-rewritable memory cells are arranged in a matrix pattern and which has a plurality of NAND memory cell units; a plurality of word lines and a plurality of bit lines which are connected to the plurality of memory cells; and a read-write control section which applies a voltage selectively to the plurality of word lines and the plurality of bit lines when writing, reading, or erasure of data into or from the plurality of memory cells is performed.
Each of the plurality of NAND memory cell units has a plurality of series-connected memory cells; a first select gate transistor connected between one end of an element consisting of the plurality of series-connected memory cells and the bit line; and a second select gate transistor connected between the other end of the element consisting of the plurality of series-connected memory cells and a source line.
The read-write control section applies a high voltage the first select gate transistor, the second select gate electrode, and the memory cells located adjacent to these gate transistors during writing or reading of data to or from the plurality of memory cells. Since the number of times a high voltage is applied is large, a change arises in the distribution of the threshold values of the memory cells, which may in turn induce erroneous writing of data.
A device described in Patent Document 1 has hitherto been known as a related-art NAND flash memory device. The related-art NAND flash memory device of Patent Document 1 supplies a word line of a selected memory cell with a write voltage for writing data into the memory cell; supplies a word line of a memory cell—which is located closer to a common source line by N (N is an integer of two or more) as compared to the selected memory cell—with a reference voltage for cutting the memory cell off; supplies respective word lines of N−1 memory cells—which are located between the word line of the selected memory cell and the Nth memory cell—with an auxiliary voltage which is lower than the write voltage; and supplies word lines of the remaining memory cells with an intermediate voltage which is midway between the write voltage and the reference voltage.
In the related-art NAND flash memory device of JP-A-2005-108404, erroneous writing of data is insufficient because of miniaturization of the memory cells.